Testing memories

ABSTRACT

Methods and apparatus to test memories, such as, for example, caches of processors, are disclosed. In one aspect, an apparatus may include a pseudo random address generation unit, such as, for example, including a linear feedback shift register, to generate pseudo random memory addresses, and a deterministic data generation unit, such as, for example, including a state machine, to generate deterministic data to be written to the pseudo random memory addresses. Computer systems and other electronic systems including such apparatus are also disclosed.

BACKGROUND

1. Field

Embodiments of the invention relate to memory testing.

2. Background Information

It may be beneficial to test memory arrays in order to detect faults,such as, for example, stuck-at faults, addressing faults, couplingfaults, neighborhood pattern sensitive faults, indepotent faults, andthe other faults. A variety of memory array testing protocols are knownin the arts.

Certain protocols, such as, for example, deterministic marches, rely onan understanding of the physical topology of the memory array. However,such information about the memories may be confidential or otherwiseunavailable, and this may adversely affect the deterministic tests.

Other protocols recognize that the topology may not be known and applyrandom address generation, random data, and random reads and writes.However, such tests may involve excessive test times and complicatedtest failure diagnostics. Additionally, such tests may have limitedability to test for addressing faults, since there may not bepredictable reads and writes to the same address.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The invention may best be understood by referring to the followingdescription and accompanying drawings that are used to illustrateembodiments of the invention. In the drawings:

FIG. 1 shows a test specification and results evaluation system, a testsystem, and a memory, according to one or more embodiments of theinvention.

FIG. 2 shows a test system, according to one or more embodiments of theinvention.

FIG. 3 shows eight sets of deterministic data suitable for one or moreembodiments of the invention.

FIG. 4 shows an exemplary unit layout of a memory, according to one ormore embodiments of the invention.

FIG. 5 shows a flow diagram of a method of testing a memory, accordingto one or more embodiments of the invention.

FIG. 6 shows a shorthand or pseudocode representation of the method ofFIG. 5, according to one or more embodiments of the invention.

FIG. 7 shows a block diagram of a computer system in which one or moreembodiments of the invention may be implemented.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth.However, it is understood that embodiments of the invention may bepracticed without these specific details. In other instances, well-knowncircuits, structures and techniques have not been shown in detail inorder not to obscure the understanding of this description.

FIG. 1 shows a test specification and results evaluation(specification/evaluation) system 110, a test system 120, and a memory160, according to one or more embodiments of the invention. Thespecification/evaluation system may specify a test to be performed onthe memory and may provide the test to the testing system. The testingsystem may receive the specified test, test the memory according to thespecified test, receive results of the test, such as, for example, passand/or fail information, and provide the results of the test to thespecification/evaluation system. The specification/evaluation system maythen evaluate the results of the test. If one or more faults aredetected, the memory may be discarded, or repaired, for example.

FIG. 2 shows a test system 220, according to one or more embodiments ofthe invention. The test system includes a control unit 225, a pseudorandom address generation unit (AGU) 230, such as, for example,including one or more linear feedback shift registers, to generatepseudo random memory addresses, an inversion unit 235, a comparatorrange/address inserter (comparator/inserter) unit 240, an address outputunit 245, a read/write control unit 250, a deterministic data generationunit (DGU) 255, such as, for example, including one or more statemachines, to generate deterministic data to be written to the pseudorandom memory addresses, and a data comparison unit 256.

The control unit may include one or more interfaces, such as, forexample, one or more test access port (TAP) interfaces, to receive testspecifications and provide test results. Potential test specificationinformation may include, but is not limited to, information on how togenerate pseudo random memory addresses (for example one or morepolynomial selections and seed values), information on how to generatedeterministic data (for example one or more data sequence selections andone or more start points), and information about the memory (for examplethe top range of the memory and/or other information about the logicaltopology of the memory).

The control unit may include control registers that may be programmed orotherwise provided with test specification information. For example, oneor more polynomials, seed values, data sequence selections, and startingpoints in the sequences may be stored in the control registers. One ormore of the control registers may be used to provide a loop counter toloop or otherwise count through a memory address space so that data maybe written to and/or read from the different addresses. In one aspect,the counter may match or otherwise correspond in size to the memoryaddress space. For example, an eleven-bit counter may be included tocount through the addresses of an eleven-bit indexed memory.

The control unit may be coupled with other components of the testsystem, such as, for example, in the illustrated embodiment, with thepseudo random AGU, the inversion unit, the comparator/inserter unit, theread/write control unit, the deterministic DGU, and the data comparisonunit. The control unit may provide information and control to thecomponents. For example, the control unit may provide testspecifications to the components. The control unit may also provide aglobal clock to control the timing, transitions, and/or states of othercomponents.

The pseudo random AGU is coupled with the control unit and may receiveinformation, controls, and/or clocking from the control unit. The pseudorandom AGU may generate pseudo random memory addresses and sequencesthereof. As used herein, a pseudo random address means an address thatmay appear to be random, but may in fact be predictable.

In one or more embodiments of the invention, the pseudo random AGU mayinclude one or more linear feedback shift registers (LFSRs), such as,for example one or more programmable LFSRs. The one or more LFSRs mayevaluate or otherwise use one or more polynomials, such as, for example,prime polynomials, and one or more seed values in order to generate thepseudo random memory addresses and sequences thereof. The polynomialsmay include mathematical functions, which may be implemented inhardware, software, or some combination, which are capable of providingindividually unique transitions through the memory address space, whichappear to be random, but which are predictable. Various suitablepolynomials are known in the LFSR arts. In one aspect, the control unitmay program the one or more programmable LFSRs with the polynomials andseed values based on test specification information and/or informationhard programmed in the control unit. Non-programmable LFSRs may alsooptionally be included and used, although they may tend to limit theflexibility and customizability of the tests.

In one aspect, the size or repeat loop of the LFSR may match orotherwise correspond with the size of the memory address space. Forexample, in one or more embodiments of the invention, in order toaddress all N-addresses of a memory address space, an N-lengthpolynomial may be used for an LFSR. However, a property of an N-lengthpolynomial includes that it may provide only N−1 unique pseudo randomnumbers/addresses, not N unique pseudo random numbers/addresses. Oneaddress of the memory address space, such as an all zero address, mayremain un-addressed.

Referring again to FIG. 2, the illustrated test system includes thecomparator/inserter unit. The comparator/inserter unit is coupled withan output of the pseudo random AGU and may receive a pseudo randommemory address. In one or more embodiments of the invention, thecomparator/inserter unit may insert an additional memory address so thatall addresses of the memory address space may be visited by the testsystem. In one aspect, an address including either all zeros or all onesmay be inserted. For example, an address including all zeros may beinserted if the output of a polynomial is used for addressing and/or anaddress including all ones may be inserted if the inverse of the outputof a polynomial is used for addressing. In one aspect, the additionaladdress may be inserted immediately after an address matches a seedvalue. The address inserter portion of the comparator/inserter unit isoptional and not required. In one or more embodiments, it is notrequired that all addresses of the memory be tested, and analysis of theresults may optionally be adapted to accommodate for the non-addressedmemory addresses.

As shown in the illustrated embodiment, a single unit may be used toperform both comparison of range and to insert a cycle, such as, forexample, in order to reuse common comparison and other functionality,although this is not required. In one or more alternate embodiments ofthe invention, separate comparator and inserter units may optionally beincluded and used.

Now, the use of LFSRs for pseudo random address generation is notrequired. In one or more alternate embodiments, a predetermined sequenceof pseudo random numbers, such as, for example, which may be generatedby a computer system running a random number generator, may be hardprogrammed in a memory, such as, for example, a RAM. The sequence may beread or otherwise provided from the memory as pseudo random addresses orsequences thereof. Other pseudo random AGUs capable of generating pseudorandom memory addresses and/or sequences that may be used to writeand/or read data to and/or from the memory may also optionally beincluded and used.

Let's discuss one further point associated with addressing before movingon to discuss data generation. Some memories have ranges that are notfully 2^(n) (for example 1, 2, 4, 8, 16, 32, etc.) in length. Whentesting such memories, the pseudo random AGU may generate memoryaddresses that are not in range. For example, the AGU may generate anaddress of 32, when the memory has a shorter length of, for example, 30.

With reference again to FIG. 2, the illustrated test system includes thecomparator/inserter unit. The comparator/inserter unit is coupled withthe pseudo random AGU via the inversion unit, and may receive a pseudorandom memory address. In one or more embodiments of the invention, thecomparator/inserter unit may compare the pseudo random memory addresswith a top range of memory addresses for the particular memory tested,which may be provided to the comparator/inserter unit by the controlunit along with other potential test specification information.

If the comparison indicates that the pseudo random memory address isless than the top range or within range, the comparator/inserter unitmay provide the pseudo random memory address as output to the addressoutput unit. Address generation may be slower than data generation andmay in some embodiments be provided with a head start. The addressoutput unit may include a pipeline or other buffer to delay output of anaddress, such as, for example, to synchronize address and data output,and then output the memory address to the memory. In one or moreembodiments of the invention, the comparator/inserter unit may provide asignal to the read/write control unit to allow reads and/or writes tothe memory. As shown, the comparator/inserter unit may be coupled withthe read/write control unit to provide such signals. Alternatively, inone or more other embodiments, reads and/or writes from the read/writecontrol unit to the memory may optionally be enabled or allowed in theabsence of a signal indicating otherwise from the comparator/inserterunit.

Conversely, if the comparison indicates that the pseudo random memoryaddress is greater than the top range or out of range, thecomparator/inserter unit may provide a signal to the read/write controlunit to stop output of the address and/or stop reads and/or writes tothe memory until a pseudo random memory address is in range. When thepseudo random memory address is determined to be out of range, thecomparator/inserter unit may also optionally provide a signal to thepseudo random AGU requesting a new address. As shown, thecomparator/inserter unit may be coupled with the pseudo random AGU toprovide such signals.

Now, the comparator range portion of the comparator/inserter unit isoptional and not required. In one or more embodiments of the invention,rather than using the comparator range portion, the AGU may be adaptedto suppress memory addresses greater than the top range. Nor is itrequired that the apparatus be capable of testing memories with lessthan 2^(n) memory addresses.

In one or more embodiments of the invention, rather than using anevaluation of a polynomial of the LFSR to generate a pseudo randommemory address, an inverse of the output or evaluation of a polynomialmay be used to generate a pseudo random memory address. The test systemoptionally includes the inversion unit coupled with the pseudo randomAGU to invert a pseudo random memory address. Using an inverse of amemory address may offer certain potential advantages, such as stressingthe memory, as will be discussed further below. However, inclusion ofthe inversion unit is optional, and not required.

Now, let's discuss generation of the deterministic data. Referring againto FIG. 2, the testing system further includes the deterministic DGU.The deterministic DGU is coupled with the control unit and may receiveinformation, controls, and/or clocking from the control unit. Thedeterministic DGU may generate deterministic and/or predetermined datathat may be written to, and optionally subsequently read from, thememory. As used herein, deterministic data means data that may bepredicted or otherwise determined from one or more preceding events. Thedeterministic data may be predetermined by the one or more precedingevents.

In one or more embodiments of the invention, the deterministic DGU mayinclude one or more state machines. The state machines may generatedeterministic and/or predetermined data according to a set of allowedstates, a start state, and allowed transitions that map current statesto next states. Given a current state and the allowed transitions, forwhich there may be exactly one transition from each current state to anext state, the next state may be determined.

FIG. 3 shows eight sets of deterministic data suitable for one or moreembodiments of the invention. Each set includes eight unique three-bitdata values, which covers all possible transitions for a three-bitsequence. Arrows are used to show allowed transitions between the datavalues. In the left-hand column of each set, from top-to-bottom, thedata values are referred to herein as D0, D1, D2, D3, D4, D5, D6, or D7.For example, in the first set, D0 has a value of 000, D1 has a value of001, and so on. In one or more embodiments of the invention, D7 may bedetermined or predetermined based on D6, D6 may be predetermined basedon D5, D5 may be predetermined based on D4, and so on. For example,within the same row, the three-bit data value listed in the right-handcolumn may represent an allowed state transition from the three-bit datavalue listed in the left-hand column. By way of example, for the firstset, 001 (D1) may follow an allowed state transition from 000 (D0), and010 (D2) may follow an allowed state transition from 001 (D1), and soon. For clarity, the scope of the invention is not limited to these setsor any set thereof.

In the case of a word oriented memory, the three-bit data values may bewritten to the cells at the same time. If the data word width is greaterthan three-bits, then the three-bits may be mapped in order from leastsignificant bit to most significant bit into the corresponding bitpositions. For example, an eight-bit word may include three at leastpartial images of the base three-bit sequence, such as, for example,11011011, where the right-most two-bits include the lower order bits andthe highest order bit, for example 0, has been removed. If the wordwidth is smaller than three-bits, then the lower order subset of bitsmay be used. By way of example, exemplary sequences of repeatingthree-bit data values that may be written into an eight-bit word include00000000, 001001000, 01001001, 01101101, 10010010, 10110110, 11011011,and 11111111.

Now, the use of three-bit data values may offer certain potentialadvantages. To illustrate, consider FIG. 4, shows an exemplary unitlayout of a memory, such as, for example, a RAM memory, according to oneor more embodiments of the invention. The layout includes nine cellsincluding a base cell, at center, and eight adjoining cells, whichsurround the base cell. Certain cell faults tend to be stimulated byreads and/or writes in which there is a dependency on the neighboringcell state. In one aspect, in order to help test the base cell forpattern sensitive faults, a large number of states, or all possiblestates, may optionally be provided around the base cell.

In one or more embodiments, in order to help test with a large number ofsurround conditions, nine cells, which may each store a bit, may bebroken up into three rows. In one or more embodiments of the invention,a three-bit data value, such as, for example, one from FIG. 3, may bewritten to the three cells above the base cell, and another three-bitdata value may be written to the three cells below the base cell, whilethe data in the three cells in the middle is unchanged. This process maybe repeated with different data values, cycling through 2×2×2 times inorder to give the eight base data values. Going through this eighttimes, such as, for example, by using all eight sets of data values, maycompletely capture all surround conditions and may go through each ofthe transition conditions for each unique data topology. This mayprovide a high probability that indempotent coupling faults may bedetected. However, the scope of the invention is not limited in thisrespect, or to any known standard or quality of testing. Subsets of suchdata values and/or inferior tests may be sufficient for otherimplementations of embodiments of the invention.

The deterministic data generation unit, which as stated may include astate machine, may generate the predetermined and/or deterministic databased on a selected set, such as, for example, set 1, and a startingvalue, such as, for example, 011. By way of example, for set 1 and astarting value of 011, the deterministic DGU may generate 100, then 101,then 110, and so on. However, the use of a state machine is notrequired. In one or more other embodiments of the invention, rather thanusing a state machine, the DGU may include a sequence of data programmedor hard programmed in a memory.

Referring again to FIG. 2, the deterministic data may be provided aswrite data from the DGU to the memory. The read/write control unit iscoupled with the control unit and may provide read and write controlsignals to the memory. In one or more embodiments of the invention, theread/write control unit may be implemented as a state machine to switchbetween controlling the read and write operations. When thedeterministic data generated by the deterministic DGU is to be writtento the memory, the read/write control unit may provide a write controlsignal to the memory.

The deterministic data may also be provided as comparison deterministicdata to the data comparison unit, which may optionally include aregister or other memory to store the deterministic data. As shown, thedata comparison unit may be coupled with the deterministic DGU toreceive the data. Alternatively, when data is to be read from the memoryto the data comparison unit, the read/write control unit may provide aread control signal to the memory. The data may then be read to the datacomparison unit. The data comparison unit may be capable of on-the-flycomparison of the read data with the data previously received from thedeterministic DGU, which may simplify evaluation of the test results.The data comparison unit is coupled with the control unit and mayprovide results of the comparison, such as, for example, indicatingwhether the comparison indicates that the data is the same or different,to the control unit, as test result information. The data comparisonunit is optional and not required. In one or more other embodiments, thedata comparison unit may optionally be omitted and the read data may beprovided to the control unit and output through the interface thereofprior to comparison and evaluation of the test results.

Many different methods of testing a memory are suitable. FIG. 5 shows aflow diagram of a method of testing a memory, according to one or moreembodiments of the invention.

The method includes writing a first predetermined data, such as, forexample, D0, to all addresses of the memory, at block 505. In oneaspect, the addresses may be visited linearly, such as, for example,starting from the base of the memory and continuing through to the end,although this is not required.

Then, at block 510, all addresses of the memory are visited using pseudorandom memory addresses generated by evaluating a first polynomial. Ateach visit of a memory address, a back-to-back sequence of operations isperformed before moving on to another memory address. In the sequence ofoperations, the first predetermined value, for example D0, is read fromthe present memory address. The first predetermined value presumablycorresponds to the previously written first predetermined value,assuming that there are no memory faults. Then, the sequence ofoperations includes writing a second predetermined data, such as, forexample D1 to the present memory address. Next, the sequence ofoperations includes reading back the second predetermined data, forexample D1, from the present memory address. Again, the written andsubsequently read second predetermined data presumably should match,assuming that there are no memory faults. The polynomial may beevaluated to generate other pseudo random memory addresses, and theback-to-back sequence of operations may be performed for each memoryaddress. If an address if visited more than once, the initial read mayfind improper data, such as, for example, D1 instead of D0, which mayhelp to detect simple addressing faults.

The initial read may help to test whether the data written to the memoryhas been properly preserved, and may, for example, help to test forstuck-at faults. A read resulting in a discrepancy with predetermineddata that was previously written may indicate a memory fault and may benoted in the test results. In one or more embodiments, the read, write,and read may be performed at speed in order to help detect certainfaults, such as, for example, write-after-read recovery faults andread-after-write recovery faults. The back-to-back read, write, readsequence at each address may also offer a potential advantage ofimproved detection of addressing faults. However, the scope of theinvention is not limited in this respect. In one or more alternateembodiments, the last read of the sequence may optionally be omitted.

Next, at block 515, all addresses of the memory are visited again usingpseudo random memory addresses generated by inverting an evaluation ofthe first polynomial, and at each visit of a memory address aback-to-back sequence is performed in which the second predetermineddata, for example D1, is read, a third predetermined data, such as, forexample, D2, is written, and the third predetermined data, for exampleD2, is read. As previously discussed, the inversion unit may be coupledwith the pseudo random AGU to receive an address, and may invert theaddress.

The inverse of the output of the first polynomial may give thecomplementary address space as the first polynomial. Using the outputsof a polynomial and the inverse of the output of the polynomial, whichdirectly follow one another, either in the mentioned order, or in thereverse order, may offer certain potential advantages, but is notrequired. One potential advantage is that this may provide acomplementary address that reverses the stress that was provided by thenon-inverted polynomial. Another potential advantage is that it mayprovide a cheap substitute for a polynomial and may help to reduce thenumber of prime polynomials that are used. However, inverting theevaluation of the first polynomial is not required. In one or more otherembodiments, a different polynomial may be evaluated to generate thepseudo random addresses.

Then, at block 520, all addresses of the memory are visited using pseudorandom memory addresses generated by evaluating a second polynomial, andat each visit of a memory address a back-to-back sequence is performedin which the third predetermined data, for example D2, is read, a fourthpredetermined data, such as, for example, D3, is written, and the fourthpredetermined value, for example D3, is read.

Next, at block 525, all addresses of the memory are visited again usingpseudo random memory addresses generated by inverting an evaluation ofthe second polynomial, and at each visit of a memory address aback-to-back sequence is performed in which the fourth predetermineddata, for example D3, is read, a fifth predetermined data, such as, forexample, D4, is written, and the fifth predetermined data, for exampleD4, is read.

Then, at block 530, all addresses of the memory are visited using pseudorandom memory addresses generated by evaluating a third polynomial, andat each visit of a memory address a back-to-back sequence is performedin which the fifth predetermined data, for example D4, is read, a sixthpredetermined data, such as, for example, D5, is written, and the sixthpredetermined data, for example D5, is read.

Next, at block 535, all addresses of the memory are visited again usingpseudo random memory addresses generated inverting an evaluation of thethird polynomial, and at each visit of a memory address a back-to-backsequence is performed in which the sixth predetermined data, for exampleD5, is read, a seventh predetermined data, such as, for example, D6, iswritten, and the seventh predetermined data, for example D6, is read.

Then, at block 540, all addresses of the memory are visited using pseudorandom memory addresses generated by evaluating a fourth polynomial, andat each visit of a memory address a back-to-back sequence is performedin which the seventh predetermined data, for example D6, is read, aneighth predetermined data, such as, for example, D7, is written, and theeighth predetermined data, for example D7, is read.

Next, at block 545, all addresses of the memory are visited again usingpseudo random memory addresses generated by inverting an evaluation ofthe fourth polynomial, and at each visit of a memory address aback-to-back sequence is performed in which the eighth predetermineddata, for example D7, is read, the first predetermined data, such as,for example, D0, is written, and the first predetermined data, forexample D0, is read.

Various prime polynomials for LFSRs are known in the arts. By way ofexample, here are four suitable prime polynomials for an 11-bit LFSR,which are suitable for implementing the above-described method:X¹¹+X¹⁰+X⁹+X⁷+1X¹¹+X¹⁰+X⁹+X⁵+1X¹¹+X¹⁰+X⁹+X²+1X¹¹+X¹⁰+X⁸+X⁶+1

These are just a few examples of four-tap polynomials. A variety ofsuitable 2, 6, and 8 tap prime polynomials, for example, are also knownin the arts.

To implement method shown in FIG. 5, the pseudo random AGU may include aplurality of polynomial registers to hold the referenced polynomials.For example, the AGU may include four registers. As another option, lessthan four polynomial registers may be used, such as, for example, if oneor more polynomials may be shifted in while one or more otherpolynomials are being used, for example with the use of a shadowregister.

Now, many modifications and adaptations to the above-described methodare contemplated. In one aspect, one or more operations may optionallybe removed from the method. For example, it is not required that aread-write-read sequence be used, although this may offer potentialadvantages, such as, for example, improved detection of addressingfaults. As another example, there is no requirement that four differentpolynomials be used. Either more or less may optionally be used. Stillfurther, it is not required that an inverse of a polynomial be used, orthat the polynomial and inverse directly follow one another, although asdiscussed this may offer potential advantages. In another aspect, one ormore operations may optionally be performed in a different sequence. Forexample, the data may be introduced backwards, such as, for example,from D7 through D0. As another example, an inverse of a polynomial maycome before its polynomial. These are just a few of the contemplatedmodifications.

Flexibility is one potential advantage of the test method disclosedabove. Different polynomials and combinations and orderings ofpolynomials may optionally be used to provide variability to the test.One or more different data sets and combinations and/or orderings of thedata sets may also optionally be used to provide variability to thetest. Seed values provide yet another avenue for varying the testcoverage. Additionally, a single set of data, such as, for example, set1, may be executed, or else different sets of data, such as, forexample, two, three, four, or more sets, may be executed. The sets maybe executed independently, such as, as segmented blocks. This may offercertain potential advantages, such as, for example, allowing thecapability to use either a short test, such as, for example, for testtime reduction, or a longer test, for more extensive memory testing.This may also facilitate analysis of the results, which are segmented bydata set.

FIG. 6 shows a shorthand or pseudocode representation of the method ofFIG. 5, according to one or more embodiments of the invention. “W”denotes writing data to the memory, and “R” denotes reading data fromthe memory. “^” denotes cycling through or visiting a full traversal ofthe memory address space. “^1” denotes cycling through or visiting afull traversal of the memory address space by using the first polynomialto generate the pseudo random sequence of memory addresses. “^1*”denotes cycling through or visiting a full traversal of the memoryaddress space by using the inverted value of the first polynomial togenerate the pseudo random memory addresses. “^2” denotes cyclingthrough or visiting a full traversal of the memory address space byusing the first polynomial to generate the pseudo random sequence ofmemory addresses by using the second polynomial to generate the pseudorandom memory addresses, and so on for a total of four polynomials, inthis particular protocol. The scope of the invention is not limited tothis particular protocol.

FIG. 7 shows a block diagram of a computer system 780 in which one ormore embodiments of the invention may be implemented. As used herein, a“system” or “computer system” may include an apparatus having hardwareand/or software to process data. The computer system may include, but isnot limited to, a portable, laptop, desktop, server, or mainframecomputer, to name just a few examples. The computer system representsone possible computer system for implementing one or more embodiments ofthe invention, however other computer systems and variations of thecomputer system are also possible.

The computer system includes a bus 782 to communicate information, and aprocessor 784 coupled with the bus to process information. In one ormore embodiments of the invention, the processor may include amicroprocessor available from Intel Corporation, of Santa Clara, Calif.The processor includes a memory, such as, for example, one or morecaches 785. In one or more embodiments of the invention, the processormay include a built-in test system 786, such as, for example, to testone or more caches.

The computer system includes a main memory 788, such as, for example, arandom access memory (RAM) or other dynamic storage device, coupled withthe bus to store information including instructions to be executed bythe processor. Different types of RAM memory that are included in some,but not all computer systems, include, but are not limited to,static-RAM (SRAM) and dynamic-RAM (DRAM).

The computer system includes a read only memory (ROM) 790 coupled withthe bus to store static information and instructions for the processor,such as, for example, a basic input-output system (BIOS) 791. Differenttypes of memory that are included in some, but not all, computer systemsinclude Flash memory, programmable ROM (PROM), erasable-and-programmableROM (EPROM), and electrically-erasable-and-programmable ROM (EEPROM). Amass storage device 794 such as, for example, a magnetic disk, zip, oroptical disc, and its corresponding drive, may also optionally becoupled with the bus to store information and instructions.

In one or more embodiments of the invention, the BIOS may includeinstructions 792 to at least partially specify a test to be performed onthe memory or one or more caches of the processor by the test system786. In one or more embodiments of the invention, the instructions ofthe BIOS may specify the test at start-up of the computer system, andthe test system may perform the test at start-up.

The computer system may also optionally be coupled via the bus with adisplay device 795, such as, for example, a cathode ray tube (CRT) orliquid crystal display (LCD), to display information to an end user. Adata entry device 796, such as, for example, a keyboard or otheralphanumeric input device including alphanumeric and other keys, mayoptionally be coupled with the bus to communicate information andcommand selections to the processor. Another type of user input devicethat may optionally be included is a cursor control device 797, such as,for example, a mouse, trackball, or cursor direction keys, tocommunicate direction information and command selections to theprocessor, and to control cursor movement on the display device.

A communication device 798 may also optionally be coupled with the bus.Communication devices are included in some, but not all, computersystems. Depending upon the particular implementation, the communicationdevice may include a modem, a network interface card, or otherwell-known interface devices, such as, for example, those used forcoupling with Ethernet, token ring, or other types of physicalattachment for purposes of providing a communication link to support alocal or wide area network, for example.

Embodiments of the invention are not limited to any particular computersystem. Rather, one or more embodiments may be used on any stand alone,distributed, networked, or other type of computer system. For example,one or more embodiments may be used on one or more computers compatiblewith NT, Linux, Windows, Macintosh, any variation of Unix, or others.

In the description above, for the purposes of explanation, numerousspecific details have been set forth in order to provide a thoroughunderstanding of the embodiments of the invention. It will be apparent,however, that one or more other embodiments may be practiced withoutsome of these specific details. In other instances, well-known circuits,structures, devices, and techniques have been shown in block diagramform or without detail in order not to obscure the understanding of thisdescription.

One or more embodiments of the invention may include various operations.The operations may be performed by hardware components, or may beembodied in machine-executable instructions, which may be used to causeor otherwise result in a general-purpose or special-purpose processor orlogic circuits programmed with the instructions performing theoperations. Alternatively, the operations may be performed by acombination of hardware and software.

One or more embodiments of the invention may be provided as a programproduct or other article of manufacture that may include amachine-accessible or readable medium having stored thereon one or moreinstructions and/or data structures. For example, instructions thatresult in a processor performing one or more of pseudo random addressgeneration, deterministic data generation, range comparison of pseudorandom memory addresses, memory address insertion, or data comparison,may optionally be included in a test system. The machine-accessiblemedium may provide the instructions, which, if executed by a machine,may cause or otherwise result in the machine to perform one or moreoperations or methods as disclosed herein. Suitable machines include,but are not limited to, computer systems, network devices, personaldigital assistants (PDAs), and a wide variety of other devices with oneor more processors, to name just a few examples. The machine-accessiblemedium may include, a mechanism that provides, for example stores and/ortransmits, information in a form that is accessible by a machine. Forexample, a machine-accessible medium may include recordable and/ornon-recordable media, such as a floppy diskette, optical storage media,optical disk, CD-ROM, magnetic disk storage media, magneto-optical disk,read only memory (ROM), random access memory (RAM), EPROM, EEPROM, Flashmemory, or combination, to name just a few examples. Amachine-accessible medium may also include an electrical, optical,acoustical or other form of propagated signal, such as carrier waves,infrared signals, digital signals, for example. One or more embodimentsof the invention may be downloaded as a computer program product,wherein the program may be transferred from one computer or othermachine to another computer or other machine by way of data signalsembodied in a carrier wave or other propagation signal or medium via acommunication link, such as, for example, a modem or network connection.

Many of the methods are described in their most basic form, butoperations may be added to or deleted from the methods. It will beapparent to those skilled in the art that many further modifications andadaptations may be made. The particular embodiments are not provided tolimit the invention but to illustrate it. The scope of the invention isnot to be determined by the specific examples provided above but only bythe claims below.

In the claims, any element that does not explicitly state “means for”performing a specified function, or “step for” performing a specifiedfunction, is not to be interpreted as a “means” or “step” clause asspecified in 35 U.S.C. Section 112, Paragraph 6. In particular, the useof “step of” in the claims herein is not intended to invoke theprovisions of 35 U.S.C. Section 112, Paragraph 6.

It should also be appreciated that reference throughout thisspecification to “one embodiment”, “an embodiment”, or “one or moreembodiments”, for example, means that a particular feature may beincluded in the practice of the invention. Similarly, it should beappreciated that in the foregoing description of exemplary embodimentsof the invention, various features are sometimes grouped together in asingle embodiment, Figure, or description thereof for the purpose ofstreamlining the disclosure and aiding in the understanding of one ormore of the various inventive aspects. This method of disclosure,however, is not to be interpreted as reflecting an intention that theclaimed invention requires more features than are expressly recited ineach claim. Rather, as the following claims reflect, inventive aspectslie in less than all features of a single foregoing disclosedembodiment. Thus, the claims following the Detailed Description arehereby expressly incorporated into this Detailed Description, with eachclaim standing on its own as a separate embodiment of this invention.

While the invention has been described in terms of several embodiments,those skilled in the art will recognize that the invention is notlimited to the embodiments described, but may be practiced withmodification and alteration within the spirit and scope of the appendedclaims. The description is thus to be regarded as illustrative insteadof limiting.

1. A method comprising: pseudo randomly generating a first plurality ofmemory addresses of a memory based on evaluation of a first polynomial;at each of the first plurality of memory addresses, initially readingdata, then writing data, and then reading data; pseudo randomlygenerating a second plurality of memory addresses of the memory based oninverting an evaluation of the first polynomial; at each of the secondplurality of memory addresses, initially reading data, then writingdata, and then reading data; pseudo randomly generating a thirdplurality of memory addresses of the memory based on evaluation of asecond polynomial, wherein the second polynomial is different than thefirst polynomial; at each of the third plurality of memory addresses,initially reading data, then writing data, and then reading data; andperforming additional pseudo random writes of data to the memory suchthat all possible surround conditions for each base cell of the memoryare captured.
 2. The method of claim 1, further comprising transitioningthrough all possible transitions for each cell surrounding each basecell.
 3. The method of claim 1, further comprising comparing a pseudorandom memory address with a top range of a memory.
 4. The method ofclaim 1, further comprising receiving a pseudo random memory address andin response inserting an all zero memory address.
 5. An apparatuscomprising: a control unit; a pseudo random address generation unitcoupled with the control unit, the pseudo random address generation unitto generate a first plurality of pseudo random memory addresses based onevaluation of a first polynomial, a second plurality of pseudo randommemory addresses based on evaluation of the first polynomial, and athird plurality of pseudo random memory addresses based on evaluation ofa second polynomial wherein the second polynomial is different than thefirst polynomial; an inversion unit coupled with the pseudo randomaddress generation unit and coupled with the control unit, the inversionunit to invert the second plurality of pseudo random memory addressesbased on control from the control unit; and a deterministic datageneration unit coupled with the control unit, the deterministic datageneration unit to generate deterministic data, wherein thedeterministic data generation unit is to generate a plurality ofdifferent sets of deterministic data sufficient to capture all possiblesurround conditions for each base cell of a memory.
 6. The apparatus ofclaim 5, wherein the deterministic data generation unit is to generatedifferent sets of deterministic data sufficient to transition throughall possible transitions for each cell surrounding each base cell. 7.The apparatus of claim 5, further comprising a comparator range unitcoupled with the pseudo random address generation unit to receive apseudo random memory address and to compare the received pseudo randommemory address with a top range of a memory.
 8. The apparatus of claim5, further comprising an address inserter unit coupled with the pseudorandom address generation unit to receive a pseudo random memory addressand to subsequently insert an all zero memory address.